1. Field of the Invention
The present invention relates to a bonded SOI substrate and a method for manufacturing the same, and more particularly it relates to a bonded SOI substrate in which gettering sites are formed in an SOI layer, and a method for manufacturing the same.
This application claims priority from Japanese Patent Application No. 2004-149707 filed on May 19, 2004, the content of which is incorporated herein by reference.
2. Background Art
As one example of bonded substrates in which two silicon wafers are bonded together, a bonded SOI (Silicon On Insulator) substrate is known. This includes an SOI layer (an active layer) on a surface of which a device is formed, a wafer for a support substrate which supports the active layer from its rear surface, and an insulating film (a silicon oxide film) buried therebetween. In the prior art, there has also been disclosed a bonded SOI substrate in which a high density n+ layer is formed by ion implantation in an n-type SOI layer.
In the following, with reference to the flow sheet of FIG. 5, a prior art method for manufacturing such a bonded SOI substrate which incorporates an n+ layer is explained.
As shown in this figure, a single crystal silicon ingot is pulled out by the CZ method in which a predetermined amount of arsenic or antimony is doped. And then, the obtained single crystal silicon ingot is subjected to block sectioning, notch processing, slicing, surface trimming, polishing a surface to a mirror finish, and the like in regular succession. By these processes, an n-type wafer 101 for the active layer of 8 inches in diameter and having a mirror finished surface is prepared (see FIG. 5 (a)). On the other hand, a similar wafer 102 for the support substrate of which the surface is smoothed to a mirror finish is prepared by the same manufacturing process as for the wafer 101 for the active layer (see FIG. 5 (b)). And then, the wafer 102 for the support substrate is placed in a thermal oxidization furnace, and an insulating silicon oxide film 102a is formed in its surface by a thermal oxidization processing.
Next, the wafer 101 for the active layer is loaded into a medium current ion implantation device, and arsenic or antimony, which is an n-type dopant, is implanted in the wafer surface under conditions in which for example, an implantation energy is 80 keV and a dose amount is 2×1015 atoms/cm2. Thereby, an ion implantation layer I is formed to a predetermined depth in the surface layer of this wafer 101 for the active layer.
After this process, the two wafers 101 and 102 are bonded together with their mirror finished surfaces facing one another at room temperature in a clean room (see FIG. 5 (c)). Thereby, a bonded wafer 103 is manufactured. Due to this bonding, a portion of the silicon oxide film 102a which is sandwiched between the wafer 101 for the active layer and the wafer 102 for the support substrate becomes a buried silicon oxide film 102b. 
Next, the resulting bonded wafer 103 is placed into a thermal oxidization furnace for bonding, and heat-treating for bonding is performed in an atmosphere of oxygen gas. A temperature for this heat-treating for bonding is 1100° C., and heat-treating time is 2 hours (see FIG. 5 (c)). Thereby, a silicon oxide film is formed over the entire exposed surface of the bonded wafer 103. At this time, the arsenic or antimony in the ion implantation layer I is diffused thermally in a vicinity of a bonded surface side of the wafer 101 for the active layer, thereby an n+ layer (a high density impurity layer) 101a is formed. As a result, if the wafer 101 for the active layer includes a buried silicon oxide (SiO2) layer 102b, the wafer 101 for the active layer has an n/n+/SiO2 structure.
Next, void detection is performed using ultrasonic irradiation. For a bonded wafer 103 to be of good quality, defective bonding regions caused by shapes of chamfered outer peripheral portions of the two wafers 101 and 102 are removed. Specifically, the outer peripheral portion of the wafer 101 for the active layer is ground from its device fabrication surface side using a metal-bonded grinding stone of #800 to #1500 grade (see FIG. 5 (d)). This grinding of the outer peripheral portion is stopped before reaching a bonded boundary surface.
Next, a remaining non-ground portion 101c is removed by alkali etching (see FIG. 5 (e)). In detail, the bonded wafer 103 is immersed into an alkaline etching solution such as KOH or the like, thereby the remaining non-ground portion 101c is dissolved (etching of the outer peripheral portion). Accordingly, the outer peripheral portion of the wafer for the support substrate 102, in detailed terms, the outer peripheral portion of the buried silicon oxide film 102b, is exposed.
Next, the surface of the wafer 101 for the active layer is ground and polished from its device fabrication surface side. Accordingly, a bonded SOI substrate is manufactured in which an SOI layer 101A having an n/n+/SiO2 structure is formed (see FIG. 5 (f)).
Here, in a device process for fabricating a semiconductor device in the SOI layer 101A of this bonded SOI substrate, a degree of contamination of metallic impurities (iron, copper, nickel, or the like) in the SOI layer 101A having the n+ layer 101a is considered to be very important. Furthermore, as a specific problem for bonded SOI substrates accompanying ion implantation, metallic contamination is caused in an ion implantation process and a subsequent high temperature heat-treating process (for example, thermal oxidation or heat-treating for bonding).
In the case in which metallic contamination caused in these processes remains in the SOI layer 101A even after product delivery, defects are generated or electrical potentials are formed in a vicinity of the surface of the SOI layer 101A, and device characteristics are deteriorated. This problem also occurs in the case in which metallic contamination is caused in the device process. As a result, a yield rate for the devices drops. Thus, in recent years there has been a demand for a gettering effect on bonded SOI substrates which prevents generation of defects and formation of electrical potentials in the vicinity of the surface of the SOI layer 101A to be exerted for a sustainable term from ion implantation through to device processing.
In a prior art, a method as described in Patent Document 1 is known as a countermeasure against such metallic contamination. In this method, along with forming oxygen precipitates over substantially the entire wafer for a support substrate which become gettering sites for metallic impurities, dislocation groups are formed in a vicinity of the buried oxide film of the support substrate wafer. All of these oxygen precipitates and dislocation groups make up an IG (Intrinsic Gettering) layer which is formed in the wafer for a support substrate.
However, according to such a prior art method for manufacturing a bonded SOI substrate, since the IG layer is formed in the wafer for a support substrate in this manner, iron, nickel, or the like in the SOI layer, of which diffusion rates in the buried oxide film are slow (cannot pass through the buried oxide film), are not easily gettered by the IG layer in the wafer for a support substrate.
Moreover, in the CZ method, dopants tend to segregate into a portion of a silicon single crystal ingot when pulling up the ingot. This segregation caused a variation in resistance (unevenness of dopant concentration) of about 25% among sliced silicon wafers (wafers for active layers). Furthermore, even in an in-plane direction of one silicon wafer, a variation in resistance of about 10% occurred. Regarding these, in a device factory, as a pretreatment prior to fabricating a device in an SOI layer of a bonded SOI substrate, a predetermined amount of dopants were implanted into the SOI layer so as to adjust the resistance in the in-plane direction of the wafer and the resistances among the wafers. As a result, manufacturing cost of the bonded SOI substrate was increased.
On the other hand, as another method for equalizing the resistance in the in-plane direction of the wafer and the resistances among the wafers, for example, a method is known in which a silicon oxide film is formed in a surface of the wafer for a support substrate and epitaxial growth of Si is conducted thereon so as to deposit the SOI layer.
However, since epitaxial growth is conducted, the manufacturing cost of this method was also high compared with a general bonded SOI substrate manufactured by simply bonding the wafer for an active layer and the wafer for a support substrate and then grinding and polishing the wafer for an active layer from its rear surface side so as to be thinned.
Patent Document 1: Japanese Unexamined Patent Application, First Publication No. H08-298589.